Mission Statement
Heronic's purpose is to architect an efficient future for computing through automated, bespoke design.
The Problem
The current landscape of AI hardware suffers from a underlying problem: poor compute occupancy. Despite peak performance of hardware rising year-on-year, the percentage of the chip performing useful computations is diminishing to below 10%. This is caused by a number of factors: the memory wall, end of Moore's law, etc. Fundamentally, the vast majority of AI chips are sitting underutilised.
The Solution
We believe the future of compute is extremely application-specific processor architectures. Instead of developing a "one-size-fits-all" chip, next generation AI applications will require bespoke processor architectures. To achieve this level of customisation, we need to move beyond the traditional semiconductor design flow, instead bringing automation further up the stack. By addressing the compute occupancy problem at the architectural level, we can unlock the full potential of future generations of technology (photonic, neuromorphic, etc.)
Our Technology
MOSAIC integrates AI models and physical constraints through our proprietary compiler, synthesising optimal hardware architectures at machine speed.
Define performance targets, power budgets, and physical area constraints (PPA).
Ingest foundry process nodes, standard cell libraries, and custom IP cores.
Apply generative design models, reinforcement learning agents, and predictive scaling.
Multi-Objective Synthesis
& AI Compiler
Evaluates billions of design permutations to synthesise the optimal hardware architecture for your constraints.
Inside Heronic
Our Partners
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